Aldec Releases xpTracer Allowing Users to Run Design Diagnosis in "Off-Line" Mode

Henderson Nevada, February 26th, 2002 -- Aldec, Inc., a leading supplier of HDL design entry and verification software for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) announced today the release of xpTracer, a powerful off-line debugging feature for Active-HDL 5.1 that eliminates the need for a constant connection to the simulator. Users can now analyze previously simulated designs in greater detail while freeing up the simulator for other tasks.

xpTracer provides a full history of signals that have been saved as an external .psd file after the simulation run has been completed. Once the .psd file has been made, users can move bi-directionally through the simulation data to mark signals of interest and isolate specific areas of the design that may require additional analysis.

This Post-Simulation Debug feature does not require a connection to the simulator because it stores a comprehensive set of simulated signals. The signals added during simulation display the complete data from the beginning of simulation without a need to re-simulate the entire design. This comprehensive record of simulation signals allows users to look for specific signals to analyze the design operation.

“The introduction of this Post-Simulation Debug feature greatly benefits our customers because it decreases simulation time and produces faster results. Storing simulation results in an external file is particularly useful in the case of very long simulation times because designers can run simulation overnight and have all the data ready to debug the next morning. Active-HDL’s Post-Simulation Debug feature gives designers the latitude to benefit from time-intensive simulation without consuming valuable design time or resources,” stated Megan Moran, Product Marketing Manager for Active-HDL.

Since designers no longer need to wait for the simulation results, xpTracer saves system designers time and makes them more productive. Another advantage of simulation results being stored in an external file is that designers can share their simulation results with members of their design team or other designers without having to engage the other party’s simulator.

Active-HDL’s Post-Simulation Debug feature supplies comprehensive simulation results without using additional PCs that would normally be required during a lengthy simulation process. Active-HDL 5.1’s Post-Simulation Debug feature is yet another innovation that lowers the cost of design verification by minimizing the number of simulators used in design verification and allowing remote analysis of simulation results.

Availability
The Post-Simulation debug feature is included in Active-HDL 5.1’s Expert Edition and can be purchased as an add-on option with Active-HDL 5.1’s Plus Edition. Active-HDL can be licensed as a keylock or floating license, which includes Aldec’s Design Project Manager, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog, or mixed VHDL/Verilog/EDIF simulation. All sales include one year of product maintenance. Active-HDL may be run on Windows 98/2000/NT/Me or XP platforms. To receive your FREE evaluation copy, contact Aldec at www.aldec.com.

About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.

Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered
trademarks are property of their respective owners
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Contact:        Megan Moran                
Aldec, Inc.                                        
(702) 990-4400 ext. 201                        
meganm@aldec.com